Implementation of Autoencoders with Systolic Arrays through OpenCL

In the world of algorithm acceleration and implementation deep neural networks’ recall phase, OpenCL based solutions have a clear tendency to produce perfectly adapted kernels in graphic processor unit (GPU) architectures. However, they fail obtain same results when applied field-programmable gate array (FPGA) This situation, along with an enormous advance new GPU architectures, makes it unfeasible defend solution on FPGA, even terms energy efficiency. Our goal this paper is demonstrate that multikernel structures can be written classic systolic arrays OpenCL, trying extract most advanced features FPGAs without having resort traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL. methodology intensive use channels (IntelFPGA extension OpenCL) for communication both data control refinement libraries register transfer logic (RTL) code improve performance base activation functions neurons and, above all, reflect importance adequate between layers implementing neuronal networks.